The present invention relates to a logic compound method and a logic compound apparatus using a register transfer level (RTL) description for a large-scale integrated (LSI) circuit including a plurality of subblocks.
In the recent development of LSI circuits, there has been broadly employed a design technique described, for example, in pages 36 to 43 of the xe2x80x9cDesign Wave Magazinexe2x80x9d (May, 1999). Specifically, functional specifications of circuits necessary for a target LSI circuit are described in RTL notation to achieve logical compound according to the RTL description to obtain optimal gate levels for an actual production process of the LSI circuit.
The RTL description will be simply described. FIG. 8 shows in a flowchart a processing flow of an LSI circuit development using an RTL description. The processing flow includes steps 81 to 84.
Step 81 receives as an input thereto functions of a target LSI circuit designed in an RTL description at a higher abstraction level. Step 82 conducts logical compound using the contents of the RTL description to convert the RTL description into a gate net list optimized for an actual production process the LSI circuit.
Step 83 conducts allocation and wiring according to the gate net list to determine positions and wiring for the actual LSI circuit and resultantly generates a mask pattern. Step 84 produces the LSI circuit using the mask pattern.
Referring now to FIGS. 9 to 13, description will be given of the RTL description, a technology library, and compound restrictions as inputs to the logical compound processing, the gate net list as an output from the logical compound processing, and a logical compound operation using these items.
FIG. 9 shows an RTL description of a model circuit, i.e., circuit A. The respective lines have meanings as below.
Line 1 of FIG. 9 represents a first point of definition of circuit A and includes a syntax rule of xe2x80x9cmodule circuit-name (port list)xe2x80x9d.
Lines 2 to 4 represent an input/output signal definition, an output signal definition, and an internal signal definition in the following syntax rules.
Line 2: input input-signal-list;
Line 3: output output-signal-list;
Line 4: wire internal-signal-list;
Lines 5 to 7 describe combinations of circuits (combined circuits) as follows.
Line 5: Description of inverter which inverts input xe2x80x9cinxe2x80x9d and outputs the inverted signal to i1
Line 6: Description of inverter which inverts input xe2x80x9cin2xe2x80x9d and outputs the inverted signal to i3
Line 7: Description of inverter which inverts input xe2x80x9cin4xe2x80x9d and outputs a resultant signal to out
Lines 8 to 11 describe a storage element, i.e., a flip-flop (FF) circuit. This flip-flop circuit has an input xe2x80x9cinxe2x80x9d and an output xe2x80x9coutxe2x80x9d and is synchronized with a rising edge of a clock signal clk.
Lines 12 to 15 similarly describe a storage element, i.e., a flip-flop circuit. This flip-flop circuit has an input xe2x80x9ci2xe2x80x9d and an output xe2x80x9coutxe2x80x9d and is synchronized with a rising edge of a clock signal clk.
Line 16 indicates an end of the circuit definition.
A compound restriction includes a circuit clock definition and an input/output delay (delay time) restriction. The compound restriction indicates delay targets of paths (signal paths between an input pin and a flip-flop circuit, between flip-flop circuits, and between a flip-flop circuit and an output pin) in the circuit to a logical compound tool.
FIG. 10 shows a concrete example of compound restrictions of circuit A. The values are represented in nanoseconds (ns).
For explanation, assume that FIG. 11 shows a relationship between a circuit represented by the RTL description of FIG. 9 and the delay targets indicated by the compound restrictions of FIG. 10.
Line 1 of FIG. 10 is a clock definition which defines that a clock signal clk has a period of 10 ns. This gives a delay target 1101 indicating the logical compound tool to construct a circuit in which delay of a signal between flip-flop circuits synchronized with the clock clk is equal to or less than 10 ns.
Line 2 of FIG. 10 is an input delay restriction. This indicates that a combined circuit 1111 having a delay of six nanoseconds exists between an external flip-flop circuit and the input port xe2x80x9cinxe2x80x9d. Therefore, this gives a delay target 1102 indicating the logical compound tool to construct a circuit in which delay of a signal from the input port xe2x80x9cinxe2x80x9d to the flip-flop circuit synchronized with the clock clk is 4 (=10xe2x88x926) ns.
Line 3 of FIG. 10 is an output delay restriction and means that a combined circuit 1112 with a delay of 1 ns exists between an output port xe2x80x9coutxe2x80x9d of the circuit and a flip-flop circuit synchronized with the clock clk. Therefore, this gives a delay target 1103 indicating the logical compound tool to construct a circuit in which delay of a signal from the flip-flop circuit synchronized with the clock clk to the output port xe2x80x9coutxe2x80x9d 9 (=10xe2x88x921) ns.
A technology library is a table including functions and parameters of logical elements (to be referred to as cells herebelow) such as an AND element, an OR element, and a flip-flop element which can be generated in the LSI circuit production process. FIG. 12 shows an example of the contents of the technology library.
First, the logical compound is achieved using the RTL description of circuit A shown in FIG. 9 according to the compound restrictions of FIG. 10. The results of the logical compound are then converted into a gate net including cells listed in the technology library shown in FIG. 12. FIG. 13 shows a gate net list resultant from the conversion.
In the gate net list shown in FIG. 13, lines 1 to 4 are the same as the RTL description of FIG. 9, namely, include a definition of a start point of module definition and definitions of input/output signals and internal signals.
Lines 5 to 9 of FIG. 13 indicate a connection relationship and a description to instance a function of a technology library cell and are described in a syntax rule of
cell name instance-name (port list);
Line 10 indicates an end of the module definition.
Line 5 is obtained by instancing an inverter 1121 of the circuit in the RTL description of FIG. 11 using an inverter invd2 cell of the technology library of FIG. 12. In the operation, the logical compound tool selects, according to the delay target 1102 that the delay from the input xe2x80x9cinxe2x80x9d to the input xe2x80x9ci1xe2x80x9d of the flip-flop element is 4 ns or less, invd2 with a delay of 3 ns from the cells invd0 to invd3 having the same function in the technology library.
Line 6 is obtained by instancing an inverter 1122 of the circuit in the RTL description of FIG. 11 using an inverter invd0 cell of the technology library of FIG. 12. In the operation, the logical compound tool selects, according to the delay target 1101 that the delay between the flip-flop elements is 10 ns or less, invd0 with a smallest area among the cells invd0 to invd3 having the same function in the technology library.
As above, when a plurality of cells satisfy one delay target, the logical compound tool selects one of the cells having the smallest area among the cells.
Line 7 is obtained by instancing an inverter 1123 of the circuit in the RTL description of FIG. 11 using an inverter invd1 cell of the technology library of FIG. 12. In the operation, the logical compound tool selects, according to the delay target 1103 that the delay between the flip-flop elements is 9 ns or less, invd1 with a smallest area among the cells invd0 and invd1 having the same function in the technology library.
Lines 8 and 9 are obtained by instancing a flip-flop element in the RTL description of FIG. 11 using a flip-flop element in the technology library of FIG. 12.
As described above, the logical compound processing interprets the RTL description and replaces a description item of a flip-flop element with a cell of a flip-flop element in the technology library of the LSI circuit production process. For a combined circuit in the RTL description, the logical compound processing implements a circuit to satisfy a path delay target indicated by the compound restrictions using the a cell in the technology library of the LSI circuit production process.
The processing above will be called xe2x80x9cgate mapping of combined circuitsxe2x80x9d herebelow.
In logical compound processing of a long RTL description, there is usually employed a partition compound method in which the RTL description is divided into partitions or subblocks each having a size suitable for the logical compound tool. The logical compound processing is then conducted for each subblock of the RTL description.
This is used because of advantages that the memory capacity required for the logical compound tool is small and the processing time is reduced. Additionally, for any modification in the results of the RTL description, it is necessary to conduct the logical compound processing only for the subblock including the RTL description. This minimizes the turnaround time (TAT) of the processing.
To carry out the logical compound for each subblock in the partition compound processing, compound restrictions are required for the subblock.
The subblock compound restrictions specifically indicate a clock definition and input/output delay restrictions and act on the subblock logical compound as below.
To conduct logical compound of an intra-subblock path between flip-flop elements in a subblock, the path delay target is calculated using a clock definition and a combined circuit in the path is logically compounded to minimize discrepancy between the delay of the path and the path delay target.
To conduct logical compound of an external path of a subblock from an external pin to a flip-flop element in the subblock, the delay value of the path and the path delay target are calculated using the input/output delay restrictions and a combined circuit in the path is logically compounded to minimize discrepancy between the delay of the path and the path delay target.
To generate the input/output delay restrictions, there may be used a method in which the designer manually generates the restrictions in consideration of the circuit configuration and a method in which, as in the xe2x80x9cinterlayer delay distribution methodxe2x80x9d described in JP-A-10-214280, the entire circuit before logical compound is accessed to obtain information of each path between subblocks as objects of the logical compound so as to automatically generate input/output delay restrictions for each subblock according to the information.
The prior art has been attended with a problem when a flip-flop element at a start point of a path and an end point thereof exist in mutually different subblocks. That is, for an inter-subblock path passing a boundary between the subblocks, the logical compound is separately carried out as an external path for each subblock. Since the delay between the inter-subblock path depends on input/output delay restrictions controlling the logical compound for each external path, there arises a problem as follows.
First, a partition compound operation using the input/output delay restrictions is conducted regardless of how the input/output delay restrictions are generated, namely, manually or automatically. The logical compound to produce combined circuits in the inter-subblock path is not carried out by checking the logical structure and the delay in the entire inter-subblock path under the logical compound operation.
Therefore, to optimize an inter-subblock path in the prior art, it is necessary to repeatedly execute processing:
Generation and modification of input/output delay restrictionsxe2x86x92Logical compound processingxe2x86x92Verification of timing for inter-subblock path.
However, even if the processing is repeatedly executed, it is not necessarily guaranteed that the value of delay of the inter-subblock path converges.
Consequently, in the prior art in which input/output delay restrictions are manually generated, the restrictions must be generated such that the difference between the delay of the inter-subblock path and the target delay is minimized. This requires a considerable amount of human power.
In the prior art in which input/output delay restrictions are automatically generated, the restrictions are generated using the RTL description in which changes in the combined circuits after the logical compound are not taken into consideration. There often arises a problem in which as a result of excessively strict restrictions, the circuit area which should be otherwise smaller is increased or in which as a result of excessively light restrictions, a violation path which should be otherwise solved remains unsolved.
It is therefore an object of the present invention to provide a logic compound method and a logic compound apparatus in which delay values of all paths can approach respective target values through one operation of processing and hence the inter-subblock paths can be easily optimized with a little amount of human power in a short period of time.
To achieve the object in accordance with the present invention, there is provided a logical compound method comprising the steps of subdividing a logic circuit described in RTL notation into a plurality of subblocks, conducting logical compound for each of the subblocks, executing intra-subblock path delay adjustment processing in which logical compound is conducted using at least a clock definition such that delay of each intra-subblock path approaches a target value thereof for each of the subblocks, and executing inter-subblock path delay adjustment processing in which logical compound is conducted using at least a clock definition such that that delay of each path selected from a group including a path between the logic circuit and one of the subblocks and paths between the subblocks approaches a target value thereof.
In accordance with the present invention, in the logical compound method according, the inter-subblock path delay adjustment processing may comprise the step of replacement processing which generates, in each of the subblocks, a combined circuit on a fan-out trace with a start point at an external pin of the subblock, a combined circuit on a fan-in trace with a start point at an external pin of the subblock, a subblock boundary section including a flip-flop element of the fan-out trace of the combined circuit, and a subblock boundary section including a flip-flop element of the fan-in trace of the combined circuit and which replaces according to an RTL description the subblocks respectively with the subblock boundary sections respectively associated therewith.
In accordance with the present invention, in the logical compound method, the intra-subblock path delay adjustment processing may be concurrently executed for the respective subblocks.
According to the present invention, an inter-subblock path can be treated as an intra-subblock path and hence no input/output delay restriction is required to compound the inter-subblock path. Therefore, performance of the logical compound tool can be fully utilized and the inter-subblock paths can be optimized through one operation of processing.